library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_mux_4to1 is
end tb_mux_4to1;

architecture BEH of tb_mux_4to1 is
    component mux_4to1
        Port ( X0 : in  STD_LOGIC_VECTOR(7 downto 0);
               X1 : in  STD_LOGIC_VECTOR(7 downto 0);
               X2 : in  STD_LOGIC_VECTOR(7 downto 0);
               X3 : in  STD_LOGIC_VECTOR(7 downto 0);
               C : in  STD_LOGIC_VECTOR(1 downto 0);
               D : out  STD_LOGIC_VECTOR(7 downto 0));
    end component;

    signal X0_tb, X1_tb, X2_tb, X3_tb : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    signal C_tb : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
    signal D_tb : STD_LOGIC_VECTOR(7 downto 0);

begin
    uut: mux_4to1 port map (
        X0 => X0_tb,
        X1 => X1_tb,
        X2 => X2_tb,
        X3 => X3_tb,
        C => C_tb,
        D => D_tb
    );

    stim_proc: process
    begin
        -- Test scenario
        X0_tb <= x"12";
        X1_tb <= x"34";
        X2_tb <= x"56";
        X3_tb <= x"78";

        C_tb <= "00"; wait for 10 ns;
        assert D_tb = x"12" report "Error at C=00" severity error;

        C_tb <= "01"; wait for 10 ns;
        assert D_tb = x"34" report "Error at C=01" severity error;

        C_tb <= "10"; wait for 10 ns;
        assert D_tb = x"56" report "Error at C=10" severity error;

        C_tb <= "11"; wait for 10 ns;
        assert D_tb = x"78" report "Error at C=11" severity error;

        wait;
    end process;
end BEH;